1. Field
Example embodiments of the inventive concepts relate to a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
In a dynamic random access memory (DRAM) device having a unit cell consisting of a MOS transistor and a capacitor, decreasing a chip area occupied by a capacitor while increasing capacitance of the capacitor is an important factor to achieve high integration of the DRAM device.
In order to form a capacitor having high capacitance in a narrow area, increasing the height of the capacitor or decreasing the thickness of a dielectric layer is being attempted.
However, in the former case, a problem may arise due to an increase in the step difference by increasing the height of the capacitor. In the latter case, leakage current may increase by decreasing the thickness of a dielectric layer.
To overcome the problems, there has recently been proposed a method for reducing the capacitance of the capacitor required to maintain the capability of a sense amplifier at the same level by reducing bit line parasitic capacitance in half using a buried type gate structure.
However, according to the tendency toward high integration, a margin between a storage node contact and a bit line contact may be unavoidably reduced.